FIELD OF THE INVENTION
This invention relates in general to a method of fabricating a dynamic random access memory (DRAM), and more particularly to a method of fabricating a node contact for a DRAM device.
It is very difficult to design the node contact in the manufacturing process of sub-micron stacked DRAM, especially when trying to avoid the shorts between the electrodes and bit lines. A method of depositing a liner oxide layer accompanied with etching back technology is used in conventional procedures to improve this problem. However, this conventional method still has some limitations, for example, the size of the contact opening is limited so that it is smaller than the width of the bit line. Therefore, as the size of the device decreases, the manufacturing process becomes more and more difficult.
FIG. 1 shows a diagram of a conventional structure. Referring to FIG. 1, an inter-poly dielectric layer 102 is formed on a substrate 100. Polycide layers 104 acting bit lines are formed on the dielectric layer 102. Then, an oxide layer 106 for isolation is formed over the bit lines 104. A contact opening 108 is formed between the bit lines 104. Liner oxide layers 110 are utilized to isolate the bit lines 104 and polysilicon layer 112 which is an electrode of a capacitor. The drawback of the conventional process is that the width of the contact opening 108 has to be smaller than the distance between the bit lines 104. Otherwise, shorts will occur on the top and corner portions of the bit lines.